1. Technical Field
The present invention generally relates to computer aided integrated circuit design systems, and more particularly to systems and methods for accurately verifying signal timing for signal paths in an integrated circuit.
2. Description of the Related Art
Integrated circuits are electrical circuits that arrange transistors, resistors, capacitors, and other components on a single semiconductor die or substrate, upon which the various components are interconnected to perform a variety of functions. Typical examples of integrated circuits include, for example, microprocessors, programmable-logic devices (PLDs), electrically-erasable-programmable-read-only memory devices (EEPROMs), random-access-memory (RAM) devices, operational amplifiers, voltage regulators, etc.
Often, circuit designs are simulated by computer to verify functionality and timing to ensure that performance goals will be satisfied. Design and circuit analysis procedures are often performed using electronic-computer aided design (E-CAD) tools. The design and subsequent simulation of a very large scale integration (VLSI) circuit or other electrical devices via E-CAD tools allows a product design to be confirmed and often eliminates the need for building a prototype. Thus, E-CAD tools may enable a VLSI circuit manufacturer to bypass costly and time consuming prototype construction and performance verification stages in the product development process.
A VLSI circuit design can be represented at different levels of abstraction using a hardware description language. Some hardware description languages support circuit descriptions at a register-transfer level, as well as at a logic level.
At any level of abstraction, a circuit design may be specified using behavioral or structural descriptions, or a combination of both. A behavioral description is often specified using Boolean functions. A structural description may include a list describing the various connections in a network of primitive or higher-level cells. Such a list is often called a “netlist.” The netlist may be used by logic synthesizers, circuit simulators, and other circuit design optimization tools to model the circuit. Examples of primitive cells are, among others, full-adders, logic gates, latches, and flip-flops. A register is an example of a higher-level (i.e., a non-primitive) cell.
A number of known systems use information provided in netlists to evaluate circuit timing and other related parameters. Although the operational specifics vary from system to system, generally such systems operate by identifying certain critical timing paths, modeling the conductors and the various cells defining each critical timing path using a resistor-capacitor (RC) network, and then evaluating the circuit to determine whether timing violations occur for signals required to traverse each of the critical paths. A static timing tool, which is a specific type of optimization tool can be used to confirm that received input signals will arrive in time for the receiving block to process the signals, and that block output signals will reach their designated destination circuits before the next clock cycle. Static timing tools are designed with a focus on cell to cell (e.g., register to register) travel time estimates.
One of the more difficult aspects of VLSI circuit design deals with the problem of how to identify and resolve circuit failures due to signal timing problems. Signal timing problems are often not identified until after each functional block designer has completed and integrated a specific functional block circuit design into a timing model. Once timing problems are identified, they are often resolved through an iterative process of redesign and retest using a static timing tool.
One factor that affects signal timing success across the various functional blocks of a VLSI circuit design is clock uncertainty. Clock uncertainty refers to an expected range of time within which the distributed clock signal will transition at any single component within the circuit. To minimize clock uncertainty (i.e., to maintain relatively tight coordination of data signal transfers), VLSI circuit designers use clock distribution schemes that attempt to simultaneously provide a clock signal to each circuit component involved in a data transfer.
A typical approach is to construct a generally symmetrical clock distribution structure with similarly constructed clock buffers to deliver the clock signal across the VLSI circuit. This approach lends itself to a relatively simple timing model once limits for the clock uncertainty are identified. However, this approach requires a complete clock distribution structure for each functional block. As a result, this approach can lead to inefficient use of available circuit area. Not only will this approach adversely impact integrated circuit efficiency, the simple timing model suitable for signal paths supplied by the distributed clock signal represents an oversimplification when linear data path structures are introduced in the integrated circuit.
A linear data path structure is a collection of logic circuits or elements connected in series. Generally, data path structures serially process each bit of a group of bits. Because the overall signal processing delay for a clock signal that traverses each of the logic circuits or elements of the linear data path structure is cumulative and because the transition time degrades for a signal received at each successive circuit or element, the clock uncertainty model does not accurately reflect signal timing relationships for signal paths that originate and or terminate within a linear data path.
In addition to the above mentioned shortcomings of applying a clock uncertainty model when analyzing signal timing relationships, these signal timing relationships become more important with increases in clock signal frequency. As the clock signal frequency increases, the corresponding shorter clock cycles increase the relative importance of signal transfer delays between elements in a linear data path structure. Moreover, static timing tools do not provide a mechanism to convey signal timing performance information for signals that traverse linear data path structures.
In light of competitive pressures to design functional VLSI circuits with confidence that functional blocks will operate as desired over time while reducing the design life cycle and development costs, it can be understood that there is a need for systems and methods that address these and/or other shortcomings of the prior art.